Re: 2 layer PCI and meeting spec

[Andrew Ircha <api@art-render.com>]

Someone mentioned that 2 layers immediately prevents you from using
BGAs. This is just scaremongering ;).

BGAs are not as hard as people often make out. For example, I reckon for
a 1.27mm pitch BGA you could probably break out a 176 pin device which
measures 19mm square in top and bottom layers. I'm sure there's quite a
few FPGAs which look like this. Mind you, I don't know how much logic
you would have left over for anything interesting.

I suppose there are lots of examples where BGAs are just impossible.

The other issues about decoupling and trace lengths I thought were
adequately covered in the PCI spec. The issue of 2 or four layers comes
down to only two issues: the amount of plane capacitance and the Zo of
traces on the plane. Plane capacitance is a bit of a red herring, as
it's so small as to be almost useless for most designs - you will always
need adequate decoupling capacitors. Zo is harder, because PCI 2.2
requests a value of about 50 ohms (40-100ohms rings a bell, but I don't
have the spec in front of me). So, if you are going to check anything
against the spec, try to calculate what Zo might be.

I think the vast majority of PCI cards are not fully compliant -
evidence this by the lack of PCI sig logos on the vast majority of
products - including motherboards. The most frequent violation on cheap
"PCI" cards are the missing power pins for unused rails, I think the PCI
spec. specifically says that all pins must be present. I suspect that
the reason for this is that exposed FR4 is very abrasive and could
damage the PCI connectors in your motherboard. Other non-compliance
issues are the lack of capacitors within a certain distance of VCC/Vio
pins.

Andrew Ircha