Re: Fw: PCI Clock

["Venkateshwarlu V" <venkateshwarluv@myw.ltindia.com>]

** Proprietary **

Hi,
PCI spec says SKEW should not be more than 1ns.It is required to provide  good shielding(guard) for clock to reduce the skew.
      Series Resistor increases the rise time, inturn affects skew.It's better to provide end termination resistor(equal to characteristic impedance) .
  Experts comments pls.

Thanks,
Venkat.V
Design Engineer(FPGA),
Larsen & Toubro Limited,
MYSORE
INDIA

>>> "dinesh" <dinesh@cosystems.com> 04/11/02 01:56PM >>>
Hi,

 Putting a serice  resistor of appropriate value at a distance of 2.5" may
help in handling reflection related issues on clock line while extending it
beyond 2.5".

Any comments on this point from Exp. Group ?

Din

----- Original Message -----
From: arvind v <v_arv@lycos.com>
To: <pci-sig@znyx.com>
Sent: Thursday, April 11, 2002 1:06 PM
Subject: PCI Clock


> Hi All,
>
> In one of my designs in Processor  pmc form factor, I need to run pci
clock(66MHz) to processor for trace length more than 7 inches (limitation of
the design).
>
> As per PCI Specs , on an expansion board I can run only 2.5 inches.
>
> What are the implications of this long length , any ideas to over come?
>
> Thanks in advance
> Arvind.
>
>
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