RE: PCI Clock

["Bearzi, Anthony" <abearzi@harris.com>]

Use a PLL based clock distribution circuit with adjustable feedback loop. In a
nutshell you adjust the trace length of the feedback loop to match the distance
between the clock output and the destination. If you do this correctly you will
see that the wave front arrives at the destination within specification. You are
using the device as a delay line. I have used the Texas Instruments CDCxxx
family of devices in an embedded PCI application and it worked very well. I
welcome feedback from the group with respect to how this may impact PCI
compliance.

Tony Bearzi

-----Original Message-----
From: arvind v [mailto:v_arv@lycos.com]
Sent: Thursday, April 11, 2002 3:36 AM
To: pci-sig@znyx.com
Subject: PCI Clock


Hi All,

In one of my designs in Processor  pmc form factor, I need to run pci
clock(66MHz) to processor for trace length more than 7 inches (limitation of the
design). 

As per PCI Specs , on an expansion board I can run only 2.5 inches.

What are the implications of this long length , any ideas to over come?

Thanks in advance
Arvind.


See Dave Matthews Band live or win a signed guitar
http://r.lycos.com/r/bmgfly_mail_dmb/http://win.ipromotions.com/lycos_020201/spl
ash.asp