Re: PCI Clock

["Vashek Weis" <vashek@ast.co.il> (by way of Daniel Weaver <dan.weaver@znyx.com>)]

Hello,

The 2.5" restriction is imposed by the maximum delay of the clock, 10 nS 
for 33 MHz PCI and 5 nS for 66 MHz PCI. If you use series resistor you will 
make the problem worse. You have to use buffers.

How do you live with the 1.5" restriction on the other signals.

Strictly comply with the length restriction on the CLK trace or your board 
will not work when you switch platforms. I have seen this lot of times.

Vashek
========

>Resent-Date: Thu, 11 Apr 2002 01:24:37 -0700
>From: "dinesh" <dinesh@cosystems.com>
>To: <pci-sig@znyx.com>
>Subject: Fw: PCI Clock
>Date: Thu, 11 Apr 2002 13:42:37 +0530
>
>Hi,
>
>  Putting a serice  resistor of appropriate value at a distance of 2.5" may
>help in handling reflection related issues on clock line while extending it
>beyond 2.5".
>
>Any comments on this point from Exp. Group ?
>
>Din
>
>----- Original Message -----
>From: arvind v <v_arv@lycos.com>
>To: <pci-sig@znyx.com>
>Sent: Thursday, April 11, 2002 1:06 PM
>Subject: PCI Clock
>
> > Hi All,
> >
> > In one of my designs in Processor  pmc form factor, I need to run pci
>clock(66MHz) to processor for trace length more than 7 inches (limitation of
>the design).
> >
> > As per PCI Specs , on an expansion board I can run only 2.5 inches.
> >
> > What are the implications of this long length , any ideas to over come?
> >
> > Thanks in advance
> > Arvind.


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