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Re: PCI Clock

"Clark, Raymond J (WBST)" wrote:
> 
..snip
>
> [1] Can anyone elaborate on my technical comment regarding PLLs and
> spread-spectrum clocks in PCs?
> 
> [2] Are the archives available in a more accessible form?  They used to be
> in zip files, which I used to download and write scripts to search locally
> when I was working in this area.
>

here's some emails which I had saved regarding SSC in PCI clocks.  I haven't researched the roboclock solution, but if it does have a mode which passes-through the input clock without PLL locking, that may solve your 33MHz issue.

Ted

	 Tue, 21 Nov 2000 08:43:12 -0700
	by zcamail04.zca.compaq.com (Postfix) with ESMTP
From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'ted.firlit@utmc.aeroflex.com'" <ted.firlit@utmc.aeroflex.com>
Cc: pci-sig@znyx.com
Subject: RE: Spread Spectrum PCI clock
Date: Tue, 21 Nov 2000 10:44:02 -0500

The PCI revision 2.2 spec does address SSC, but only for 66MHz operation.
For 33MHz PCI, SSC is unlimited.  The reason being, that the 33MHz clock has
always been allowed to change frequency at any time, skip cycles, and even
fully stop.

No PLL in the world can track that.

Which is why a PLL should never be used on a marketable PCI card designed
for the 33MHz PCI spec.  Sorry.

By definition, the SSC on a 33MHz motherboard is unlimited, in both
modulation rate and deviation (except that the period should never be less
than 30ns).

Andy

	 Tue, 21 Nov 2000 08:10:13 -0700
From: Keith Jasinski <jasinski@mortara.com>
To: ted.firlit@utmc.aeroflex.com
Subject: RE: Spread Spectrum PCI clock
Date: Tue, 21 Nov 2000 09:14:08 -0600
	charset="iso-8859-1"

If you are using this card in an embedded system where you have complete
control over the motherboard, you might find a solution.  If you are
planning to sell this card in the open market where you have no control over
the motherboard it is being plugged into, you are in deep trouble.  The
clock on a 33MHz PCI bus can go from 1 Hz to 33MHz in 1 clock cycle and to
any frequency in between clock cycle to clock cycle.  Using a PLL to do
clock derivation from the 33MHz is explicitly forbidden for just this
reason.

Good luck!

Keith F. Jasinski, Jr.

The comments expressed here are those of the employee and do not reflect
those of his employer.

-----Original Message-----
From: Ted Firlit [mailto:firlit@utmc.aeroflex.com]
Sent: Tuesday, November 21, 2000 8:43 AM
To: pci-sig@znyx.com
Subject: Spread Spectrum PCI clock


I am currently trying to fix a PCI card design on which I used a
Motorola
MPC931 PLL to multiply the 33Mhz clock to 100Mhz, and also provide 33Mhz
to 2 inputs on the PCI interface device.  This works fine in
motherboards without
spread spectrum, but does not lock proper phase with spread spectrum. 
Motorola FAE's are currently trying to determine an input spec for me
(modulation freq and % of freq deviation(modulation width)).

I noticed that the PCI 2.2 spec addresses SSC, but have just ordered it
so I don't yet know the details. 

I also noticed Cypress has "spread aware" PLL's, but no specs on the
modulation freq or width of the input clock.  Does anyone have
information on the limits of these parameters in current PC
motherboards?  I see that the ICS9148 clock generation part will allow
selection of up to 4% modulation width-- is this being selected in
motherboards?

What downstream PLL's are being successfully used with SSC?  Any use of
66Mhz to 100Mhz freq multipliers besides the Motorola 931 and 972?

Thanks for any info,

Ted Firlit
firlit@utmc.aeroflex.com
UTMC Microelectronic Systems
Colorado Springs, CO 80907

	 Tue, 21 Nov 2000 10:10:28 -0700
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	 for <ted.firlit@utmc.aeroflex.com>; Tue, 21 Nov 2000 12:11:06 -0500 (EST)
From: MMMEI@aol.com
Date: Tue, 21 Nov 2000 12:11:06 EST
Subject: Re: PCI spread spectrum clock
To: ted.firlit@utmc.aeroflex.com

In a message dated 11/20/00 4:11:18 PM Pacific Standard Time, 
firlit@utmc.aeroflex.com writes:

> I came across your posting in the pcisig.com/reflector regarding spread
>  spectrum clocks.  Did you ever get any answers? 
>  
>  I am currently trying to fix a PCI card design which I used a Motorola
>  MPC931 PLL to multiply the 33Mhz clock to 100Mhz, and also provide 33Mhz
>  to 2 inputs on the PCI device.  This works fine in motherboards without
>  spread spectrum, but does not lock proper phase with spread spectrum. 
>  Motorola FAE's are currently trying to determine an input spec for me
>  (modulation freq and % of freq deviation).
>  
>  I just saw that the PCI 2.2 spec addresses SSC, but have just ordered it
>  so I don't yet know the details. 
>  
>  Please write back if you have any suggestions.
>  

Hi Ted-

I came away from that discussion believing that PCI spec 2.1 technically 
disallowed PLL's in the clock path.  PCI ver 2.2 may have addressed this 
problem as you have said, but I haven't looked at the issue since I finished 
up that particular card.

Since our product was intended for an imbedded application, we ended up using 
a CPU (Intel 80960RP) with a PLL in its clock path anyway as we could control 
the types of systems in which it would be installed.  Are the spread spectrum 
systems your products are having trouble with only used for 
testing/compliance, or must your final product work with a spread spectrum 
clock?

Good Luck.

Best Regards,

-Mike Martin
Millennium Engineering, Inc.

	 Wed, 29 Nov 2000 17:51:00 -0700
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Date: Wed, 29 Nov 2000 18:53:53 -0600
From: Patrick Maupin <pmaupin@speakeasy.net>
To: ted.firlit@utmc.aeroflex.com
Subject: Re: PCI clock distribution
References: <3A256EBC.43FB1D35@utmc.aeroflex.com> <3A258237.47ED8F4B@speakeasy.net> <3A258CED.A6713219@utmc.aeroflex.com>

Yeah, all motherboards that I know of
will give you a dedicated clock, so
connecting two devices shouldn't be
a real problem (again, given that
it's not a mass-market board).

You can probably even counteract the
capacitance somewhat by reducing the
mandated 2.5" (if memory serves) clock
trace length on the board.

Running a dedicated 100MHz oscillator
will probably save you a lot of headaches,
once you get past the clock domain crossings.

Good luck!

Pat


Ted Firlit wrote:
> 
> Pat,
> 
> Thanks for the response!
> 
> Patrick Maupin wrote:
> >
> > What are you trying to do?
> 
> Sometimes I wonder...
> 
> I've got an existing PCB with a Motorola MPC931 PLL receiving the PCI
> clk and sending two 33/66Mhz outputs to my PCI device (GT64120A).  This
> Galileo device needs 2 clks for 64bit operation unfortunately, which
> violates the PCI spec.
> 
> Also the MPC931 multiplies the PCI clk by 1.5 or 3 to obtain ~100MHz for
> use on my target board.  I've found that the MPC931 does not keep phase
> locked on 33Mhz spread-spectrum motherboard clks...  then I became aware
> that the PCI spec allows the PCI-CLK to vary cycle to cycle making it
> unusable with a PLL on the target board.
> 
> Therefore, I am redesigning the PCB with a 100Mhz oscillator, and am
> sending the PCI-CLK directly to the 2 inputs on the PCI device (thus
> violating the spec, but don't I usually have a dedicated motherboard
> clock anyway?)  The total input pin capacitance should be 14.4pf, not
> too high + PCB trace capacitance.  If there's a small buffer available,
> it might be worth staying within the PCI spec.
> 
> I like your roboclock idea the best, our MOT PLL does not have a
> pass-thru mode, with the output clk at the same speed.
> 
> Thanks,
> 
> Ted
> >
> >    - If you are implementing a single PCI device in
> >      multiple PALs (each PCI signal only going to
> >      a single PAL), you might consider consolidating
> >      to a single larger CPLD or FPGA.
> >
> >    - If you are implementing multiple PCI devices,
> >      (e.g. a single PCI signal going to more than
> >      one package) you are violating the spec anyway,
> >      and violating it on the clock signal as well
> >      (e.g. for an in-house card) might not be such
> >      a bad thing, depending on how many loads you
> >      are talking about.
> >
> >    - If you need to clock devices besides the PCI
> >      interface from a single clock, you might consider
> >      deliberately introducing enough delay on a
> >      regenerated PCI clock out the back of your PCI
> >      interface to keep things from getting confused.
> >
> > If none of these solutions work, I'd look at some
> > of the motherboard PCI clock generator chips, e.g.
> > from Pericom, National, etc.
> >
> > Also, you could consider making your board modal,
> > with a way to switch a PLL in/out (perhaps using
> > one of the Robo-clock style chips).  For 33MHz
> > operation, you would keep the PLL turned off,
> > and eat the delay, which shouldn't be too bad
> > at those speeds.  For 66MHz operation, you would
> > switch the PLL on, and it would perform delay
> > compensation for you.
> >
> > Pat
> >
> > Ted Firlit wrote:
> > >
> > > Hello all,
> > >
> > > Since the PCI spec requires only one load on the PCI-CLK signal, has
> > > anyone found a buffering device which would allow multiple destinations
> > > on a target card?  Requirements would be:
> > >
> > >  - up to 66Mhz input clock
> > >  - 5V and 3.3V input tolerance
> > >  - 3.3V output voltage
> > >  - 12pf max input capacitance, output drives >= 20pf
> > >  - little delay through device (~500 psec)
> > >  - passes Spread Spectrum with low skew
> > >
> > > Thanks for any help you may have.
> > >
> > > Ted