Peer-to-peer transactions

["Francois Barlow" <fbarlow@matrox.com>]

Hi,

I'd like to point on a restriction that is fairly new to me, and I'm curious
to see how known this issue is from the PCI community.

Our applications involve several of our PCI boards to communicate with each
other (using PCI memory write and memory read transactions).  We notice that
in some systems, with several of our boards connected in them, it was
impossible for a PCI master to access a PCI target device located on a
different PCI bus segment.

As an exemple, the Intel 82860 chipset (Memory Controller Hub) uses 3
different Hub interfaces to create PCI bus segments in order to accomodate
several PCI devices.  The MCH is not able to handle PCI transactions between
two PCI devices that are respectively located behind Hubs A and B.  These
devices can only communicate with the system memory or with an other PCI
device located on the same bus segment (some other documented constraints
exist).  That is, peer-to-peer transactions crossing PCI bus segments is not
possible in all configurations.

Section 1.5 of the PCI spec (revision 2.3) says that one benefit of the PCI
local bus is the flexibility that allows "Full multi-master capability
allowing any PCI master peer-to-perr access to any PCI master/target".

I'd like to have some feedback on this, because I think that we are not the
only one concerned by this restriction.  I'm also curious to know how many
systems don't support peer-to-peer transactions.  In a matter-of-fact,
writting to system memory before requesting the Host to transfer the data to
the correct PCI device is not a very efficient alternative.

Thank you,

Fran輟is.

**********************************
Fran輟is Barlow
Asic Design Leader
Matrox electronic systems
Imaging department
tel: 514-685-7230 x2280
fax: 514-822-6110
email: fbarlow@matrox.com
**********************************