Re: Peer-to-peer transactions

["Peter Marek" <peter.marek@marekmicro.de>]

Hi,

PCI definitively supports peer to peer communication, even across bridges.
If the specific INtel devices do not support it, than this is a *special
feature* as people say nowadays. I would call it a bug. If it really behaves
like this and may not be configured to be fully transparent.

regards,

Peter Marek
General Director
MarekMicro GmbH
tel.: 049-9621-9732-110
fax: 049-9621-9732-199
www.marekmicro.de

----- Original Message -----
From: "Paul Capes" <pcapes@ics-ltd.com>
To: "Francois Barlow" <fbarlow@matrox.com>
Cc: <pci-sig@znyx.com>
Sent: Thursday, April 18, 2002 5:41 PM
Subject: Re: Peer-to-peer transactions


> Hi all,
>
> I too have started looking at peer-to-peer capability of PCI devices, and
am
> quite confused about how to proceed. The software guys are telling me that
there
> is no mechanism in the NT operating system that allows this to occur. Can
> someone comment?
>
> Francois Barlow wrote:
>
> > Hi,
> >
> > I'd like to point on a restriction that is fairly new to me, and I'm
curious
> > to see how known this issue is from the PCI community.
> >
> > Our applications involve several of our PCI boards to communicate with
each
> > other (using PCI memory write and memory read transactions).  We notice
that
> > in some systems, with several of our boards connected in them, it was
> > impossible for a PCI master to access a PCI target device located on a
> > different PCI bus segment.
> >
> > As an exemple, the Intel 82860 chipset (Memory Controller Hub) uses 3
> > different Hub interfaces to create PCI bus segments in order to
accomodate
> > several PCI devices.  The MCH is not able to handle PCI transactions
between
> > two PCI devices that are respectively located behind Hubs A and B.
These
> > devices can only communicate with the system memory or with an other PCI
> > device located on the same bus segment (some other documented
constraints
> > exist).  That is, peer-to-peer transactions crossing PCI bus segments is
not
> > possible in all configurations.
> >
> > Section 1.5 of the PCI spec (revision 2.3) says that one benefit of the
PCI
> > local bus is the flexibility that allows "Full multi-master capability
> > allowing any PCI master peer-to-perr access to any PCI master/target".
> >
> > I'd like to have some feedback on this, because I think that we are not
the
> > only one concerned by this restriction.  I'm also curious to know how
many
> > systems don't support peer-to-peer transactions.  In a matter-of-fact,
> > writting to system memory before requesting the Host to transfer the
data to
> > the correct PCI device is not a very efficient alternative.
> >
> > Thank you,
> >
> > François.
> >
> > **********************************
> > François Barlow
> > Asic Design Leader
> > Matrox electronic systems
> > Imaging department
> > tel: 514-685-7230 x2280
> > fax: 514-822-6110
> > email: fbarlow@matrox.com
> > **********************************
>
> --
> Paul Capes
>
> Interactive Circuits and Systems Ltd.
> 5430 Canotek Road
> Ottawa, Ontario
> Canada K1J 9G2
> Tel (613) 749-9241
> Fax (613) 749-9461
> Email pcapes@ics-ltd.com
>