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Re: New PCI card developing
>To: firstname.lastname@example.org, email@example.com
>Subject: Re: New PCI card developing
>Date: Thu, 25 Apr 2002 14:30:02 +0100 (BST)
>I have used the QuickLogic products with great success.
>The PCI cores are fabricated on the silicon so you don't have any PCI place
>and route issues.
I have done my own synthesizable Verilog RTL target/initiator PCI IP
core, and after months of struggle, I can meet 33MHz PCI's Tsu < 7ns with
only a few minutes of automatic P&R with Spartan-II-5, although 36 FFs have
to be handplaced far away from the pins to prevent a positive hold time.
That only takes about 5 minutes, and another 5 minutes or so to reP&R the
Furthermore, Xilinx or Altera PCI IP cores come with placement constraint
information, so as long as dealing with 33MHz PCI and a fairly new device, I
strongly doubt that P&R is going to be a big issue.
>They have a suite of parts from 32bit targets through to 64bit
> They correctly support universal card design by using dedicated VIO pins
I believe a universal PCI card is going to be a must for PCI 2.3, so
QuickPCI users will likely not have to do anything.
I don't know what Xilinx or Altera is going to do about the universal card
I know that if a PCI card with Xilinx or Altera-based FPGAs have two bit
streams, one for 3.3V PCI and one for 5V PCI, it can be a universal card,
but the PCI card will need an external chip (I saw a company called
Nallatech using a CPLD to do that.), and is Xilinx or Altera going to
release the HDL code as a reference design for such a CPLD?
>and don't have the inherent problem of SRAM configuration (which > often
>exceeds the PCI reset period).
I don't own an oscilloscope, but I have never observed that problem
with Spartan-II XC2S150.
I suppose one nice thing about OTP device is that the design is
secure, although I am sure it is costly during the development.
Kevin Brace (In general, don't respond to me directly, and respond within
the mailing list.)
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