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RE: New PCI card developing
>I believe you're over characterizing two issues. One is place and route
>with PCI. As with any FPGA, place and route is an "issue", but the parts
>are just so fast now, that place and route "issues" for PCI 33 at least,
>aren't really an issue.
I totally agree with that.
When using a fairly new FPGA like Xilinx Spartan-II, P&R is not a big issue
as long as the designer designed the logic carefully.
>The Xilinx core is fully mapped and placed, so at least with that core,
>isn't an issue. Certainly if one is developing one's own PCI interface,
>depending on the level of FPGA experience, it may be an issue. I don't
>believe this is particular to PCI though, but to FPGA design in general.
Having done my own PCI IP core from not knowing anything about HDL
or FPGAs, I can say that understanding what the synthesis tool is doing is
Several months ago, my PCI IP core had many levels of LUT for the paths not
meeting Tsu < 7ns, and I didn't understand why.
I even blamed XST (Xilinx Synthesis Technology, ISE WebPACK's synthesis
tool.) for my problem, and wished I can use Synplify, but after looking at
the LUTs being generated through a floorplanner, I realized that some paths
had too many number of inputs, therefore, unregistered inputs were being
forced to travel more levels of LUTs, thus causing Tsu violations.
I simplied the architecture and reduced the number of inputs, and since
then, I have reduced levels of LUT to a point where setup time can be met
without resorting to manual placement. (Still have to place 36 FFs away from
the pin to avoid a positive hold time.)
So, whoever else going a PCI IP core for an FPGA right now and struggling to
meet Tsu should find ways reduce the number of unregistered inputs, and if
that's not enough, handplace the LUTs in the paths not meeting Tsu.
What I found was that unregistered paths must not exceed a 3 to 4 levels of
4-input LUTs, but longer signal paths will have to be 2 levels or less.
Kevin Brace (In general, don't respond to me directly, and respond within
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