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RE: New PCI card developing
>From: "Austin Franklin" <firstname.lastname@example.org>
>To: "Kevin Brace" <email@example.com>
>Subject: RE: New PCI card developing
>Date: Thu, 25 Apr 2002 18:00:54 -0400
> > First of all, although FLEX10KE-1 supports 5V PCI, APEX20K doesn't
> > officially support 5V PCI. (The APEX20K datasheet says it does,
> > but Altera
> > website admits that APEX20K can drive only 8-loads, 2-loads short of the
> > requirement.
>There is no "10 load" requirement in the 2.1+ spec. That, if I remember
>right, was part of old specs. It's the V/I curve that's important.
PCI 2.2 specification 4.1.2 Dynamic vs. Static Drive Specification
seems to imply that a 'typical' system will have 10 loads. (8 loads for 4
expansion slots and 2 load for two motherboard devices.)
I am curious, which part of the specification does it say that a motherboard
can have more than 10 loads?
I have seen many PCI motherboards with 5 or 6 PCI slots.
> > If someone doesn't believe me, I will get the URL that says
> > that for you.)
>I would like to see exactly what they have to say...
Here is the URL.
Regardless, I still don't think Altera's devices are that PCI friendly
because of their IOE.
APEX-II/Mercury/Stratix fixes the problem of having only a single FF per
IOE, but that's too late for people who deal with 5V PCI . . .
> > ...I will
> > guess that
> > you will have a much easier time with Spartan-II meeting PCI
> > timings since
> > my PCI IP core can meet 33MHz PCI timings with only 36 FFs having to be
> > placed near the center of the chip to prevent a positive hold time. (Th
> > 0ns in PCI.)
>What's this about? All your PCI signals should be registered in the
>IOBs...you only need a few raw input signals (and the registered versions
I do use IOB FFs when I think they are useful, but I don't when I
think they will kill the timings.
Austin, I don't know how you did yours, but wouldn't it be very hard or
impossible to meet 66MHz PCI's Tsu < 3ns in Virtex/Spartan-II if you used
IOB OE (Output Enable) FFs for AD[31:0] and C/BE#[3:0]?
In my design, I don't use IOB OE FFs for AD[31:0] and C/BE#[3:0], but
instead I use a single FF for OE of AD[31:0] and another single FF for
I believe Xilinx and Altera use the same technique in their PCI IP cores
very likely to meet 66MHz PCI's Tsu < 3ns.
> > although 36 FFs have to be handplaced far away from the pin to prevent a
> > positive hold time.
>Again, I do not believe this is necessary at all. I've designed over a
>dozen PCI cores in FPGAs (as well as the first one for Xilinx), and the IOB
>timing makes PCI timing with no problem with the signals registered in the
The 36 FFs I am talking about goes to the backend interface, and
doesn't go through any LUTs, so I guess I can push them into IOBs, but so
far I didn't feel like doing that.
Unlike LUTs where the name changes each time changes are made to the HDL
code, the 36 FFs' name don't change at all after synthesis, so once I place
them somewhere on the chip, it will just stay there even when I make
modifications to my HDL code.
Kevin Brace (In general, don't respond to me directly, and
respond within the mailing list.)
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