PCIX 1.0a, page 49, top paragraph contains an implementation note that reads as follows:
"If a burst transaction crosses the first 4 GB boundary (i.e., the boundary between memory locations for which the upper 32-bit of the address are 0 and locations for which they are not), the Sequence begins with a single address cycle (see Section 2.12.1). If the Sequence is disconnected and resumes beyond the first 4 GB boundary, the continuation transaction requires a dual address cycle..."
I looked for a similar note or specification in PCI 2.3 (I searched the document) and I cannot find any. I did find in section 3.9 "64-bit Addressing" several statements to force 64-bit devices and 32-bit devices to use SAC when the address is >= 32-bit and DAC when the address is <= 64-bit, but nothing at all like the above statement linking a continuation of a burst following a disconnect. Does anyone know the reason that statement is there and if it does or does not apply to PCI 2.3?
Thanks in advance,
-rob