Re: problem with 21052-AB

["Alexander Bezrukov" <alb_@pisem.net>]

Hello Hennie van de Poel,

it is very important to know, what the core logic bridge is in
that DELL computer. Your 1.5ms seems to be a temporary
deadlock with something discarded in, say, 2^15 clocks
(2^15 PCI clocks @33MHz, indeed, is about 993us).
It could be previous delayed transaction discarded by
the core logic bridge, and the Discard Timer expiration
could lead to resetting arbiter and thus recovery from
the deadlock. But all this is only assumptions, it is
necessary to know the core logic bridge behaviour, too.

Very known issue of 21052 (Rev. A and Rev. B, but not
Rev.C) is described in Digital Semiconductor ec-qpjha-te
document. See, for example,
http://netserv2.chg.ru/packages/NetBSD/misc/dec-docs/ec-qpjha-te.ps.gz,
but this leads to endlessly repeated retries.

You can disable posting by set bit 1 of configuration register 0x40
of 21052 and see, if the problem disappear (of course, perfomance
will degrade). It might help to isolate the problem.

> I have a pci master\target in a PLD when i try this an computer
> with a 21052-AB bridge(DELL PC) when i setup a master write
> to the memory i see a burts on the secondary bus, when this is
> longer the 8 bits a stop is generated by the bridge

8 data phases, you mean?

> and the de devsel doesn't respond then any more, for almost 1.5
> ms second, then the next small burst is accepted by the bridge.

whose devsel? whom respond?

Regards,
Alexander Bezrukov



> when  the board is put in another pc every things work fine.
>
> anyone some sugestions
>
> regards
>    Hennie van de Poel
>
>
>
> --------------------------------------------------------------------------
-----------------------------------------------------------------
> Ing. H.J. van de Poel                                    Address :
Philips Research Laboratories Eindhoven
>
Building   WZ k 207 (Postbox WZ91)
> Phone     : +31-40-27-43094
Prof. Holstlaan 4
> Fax           : +31-40-27-42081
5656 AA  Eindhoven
>
The Netherlands
> Mailto:hennie.van.de.poel@philips.com