OK, now I'm really confused with respect to the specification. R2.3 pg 146 states Pins labeled +3.3(i/o) and +5(i/o) are special power pins for defining and driving the PCI signaling rail on the Universal add-in card. On the system board, these pins are connected to the main +3.3V or +5V plane, respectively."
In a 32-bit backplane these are A10, A16, B19, A59, B59.
Thanks,
Jim Stevens
-----Original Message-----
From: Phipps, Michael [mailto:michael.phipps@intel.com]
Sent: Wednesday, May 29, 2002 8:56 AM
To: 'Ingraham, Andrew'; Carter Buck
Cc: Jim Stevens; pci-sig@znyx.com
Subject: RE: PLX 9080 in 3.3V signaling environment
I think the point is that vio and power are separate. Andy is right that
whatever bus you plug into supplies 3.3 or 5 volts for vio. It is a clamp
only. Not a supply.
Mike Phipps
Intel Corp.
-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@hp.com]
Sent: Wednesday, May 29, 2002 8:39 AM
To: Carter Buck
Cc: Jim Stevens; pci-sig@znyx.com
Subject: RE: PLX 9080 in 3.3V signaling environment
Um, something MUST connect to the PCI's Vi/o lines in order to be compatible
with both 3.3V and 5V signaling environments.
If you don't connect to Vi/o, you cannot claim to comply with the PCI specs
in both environments.
It can be as simple as using Vi/o to control the clamps within the IC,
because the clamping MUST change depending on whether it is a 3.3V or a 5V
environment. If the clamping doesn't change, you are not PCI compatible.
Regards,
Andy
> ----------
> If you power the 9080 PCI buffers from the 3.3V supply then the PCI
> signaling is compatible with both 3.3V and 5V environments. These power
> pins (VDDH) must not connect to the PCI Vio lines.
>