When does Intel 860 chipset disconnect bursts to memory?

Dear PCI developers,

I'm debugging a PCI board, designed for data acquisition, on a 33MHz PCI Bus slot (Motherboard features: Intel XEON 1,5 GHz, Intel 860 Chipset).

My PCI card can transfer data to the board (target access) and from the board to main memory.

I'm experiencing a master transaction termination (disconnect with data) with the Intel PCI bridge (Intel ICH2): a target usually issues a disconnect if it's unable to transfer additional data in the transaction and I wonder when it happens in this Intel PCI Bridge.

Does anyone know which is the behaviour of Intel 860 Chipset when detects a master device claiming the 33 MHz PCI bus for a master burst write transaction to main memory? Which factors affect the burst length limit? Are there any IOQ or posting buffers overflow conditions or memory boundary limits causing a master to be preempted by this chipset?

I can not find this information neither in the product data sheet nor in Intel support team.

Thanks for help.