Re: Interrupt Disable / Status Bit: PCI 2.3

["Ben Buchanan" <Benjamin.Buchanan@nsc.com>]

Hello,

I did not see a response to these questions, and I'm curious about #2 as well. 
The spec seems unclear; though it refers to when the INTx# signals may be
asserted related to the Interrupt Status bit, the definition does not
specifically indicate that the bit applies to a particular method of signaling
interrupts.

Thanks,

Ben Buchanan
National Semiconductor Corporation



Parag Birmiwal wrote:
> 
> Reference PCI Specifications 2.3, Interrupt Disable bit 10, device control
> register and Interrupt Status bit 3, device status register.
> 
> I have the following questions:
> 
> 1.  Does the interrupt disable bit affect the MSI operations?  If a PCI
> device is configured for MSI operation and the interrupt disable bit is set
> to "1" is the PCI device required to mask generation of MSI cycles?
> 
> 2. If a PCI device is configured for MSI operations does the MSI operation
> affect the interrupt status bit?  As per the specifications, the interrupt
> disable bit is a don't care for the interrupt status bit to be set.
> 
> Regards
> 
> Parag Birmiwal
> IBM Microelectronics Division -- Austin
> Phone: 512-838-6493   Tie Line: 678-6493