Re: Non registered outputs in PCIX Mode?

[Mario Michael da Costa <mario@controlnet.co.in>]

Parag Birmiwal [24/06/02 20:08 -0500]:
> Does the PCIX (mode 1 or mode 2) require all the outputs MUST BE generated 
> of a flip-flop?  That is NO additional logic gates after the flip flop and 
> the chip pin except  the boundary scan mux and the I/O driver?  Or is it a 
> recommendation to meet the tight timings (Tval(max) = 3.8ns for 133MHz) on 
> the outputs?
> 
> Does it really matter if the output is generated of a flip-flop or 
> combinational logic if the timings are met for the PCIX mode?
> 
> Regards
> 
> Parag Birmiwal
> IBM Microelectronics Division -- Austin
> Phone: 512-838-6493   Tie Line: 678-6493

no, it shouldn't matter. IMHO the registering of output's and input's was
done keeping timing constraints in mind. if you go through the protocol,
certain aspects like target initial wait states have to occur in pairs etc.
are there because of the registering of inputs/outputs/io's. so if you meet
the timings and functionally you follow the protocol, i don't see any
problem. given that the protocol is adapted to the registering of output's
though it is hard to imagine why you wouldn't want to do this. even with a
pure registered output the 3.8 ns would only just about meet the timing
specs. maybe a 2 level logic such as a mux after the register could be
squeezed in *shrugs*.

Thank You,
Regards,
mario
					
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