[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: PCI 66MHz 5V Signaling environment?
> I thought the problem with the Intel clamping was on the BC version
> of the bridge.
Then a different problem showed up in the BE that also used the same
work around for many different reasons.
> I didn't check myself, but are you sure that comment about P_VIO applies
> to the BE version you mentioned. ("performance" means "signal integrity"
> (errata 4, in the intel doc)
Errata 4 (BC) was signal integrity. Errata 9 (BE) was performance.
Performance due to an internal miscompare resulting in many retry
Didn't lose data but did get lower performance.
> (people can feel free to chime in about the BC version. I'm interested
> in other people's experience with it's clamping issues)
We aren't making the AC/BC parts now. It would still be good historical
> Resent-Date: Thu, 25 Jul 2002 02:04:31 -0700
> X-Authentication-Warning: electra.znyx.com: list set sender to
firstname.lastname@example.org using -f
> Subject: PCI 66MHz 5V Signaling environment?
> MIME-Version: 1.0
> X-MimeOLE: Produced By Microsoft Exchange V6.0.4712.0
> Thread-Topic: PCI 66MHz 5V Signaling environment?
> Thread-Index: AcIzuH4k/kbrKbGAQWiMfzXzlMOyBQ==
> To: <email@example.com>
> X-DCC-znyx.com-Metrics: enforcer.znyx.com 1058; Body=1 Fuz1=1 Fuz2=1
> X-MIMETrack: Itemize by SMTP Server on rollsroyce/Znyx(Release 5.0.7
|March 21, 2001) at 07/25/2002 01:55:30
AM, Serialize by Router on rollsroyce/Znyx(Release 5.0.7 |March 21, 2001) at
07/25/2002 01:55:31 AM, Serialize
complete at 07/25/2002 01:55:31 AM
> content-class: urn:content-classes:message
> Resent-Message-ID: <Jk8ggB.A.BeB.4z7P9@electra>
> Resent-From: firstname.lastname@example.org
> X-Mailing-List: <email@example.com> archive/latest/8960
> X-Loop: firstname.lastname@example.org
> Resent-Sender: email@example.com
> I have to design a PCI motherboard with the Intel21154BE PCI bridge on
> it. The primary PCI bus has to work at 66MHz (64bits) and the secondary
> PCI bus at 33MHz (32bits).
> My problem is that our customer requires for the primary PCI bus a
> signaling environment of 5V (VI/O = +5V, PCI connectors 64bit, 5V). This
> would be against the PCI Local Bus Specification, which says that a PCI
> 66MHz bus uses a +3.3V signaling environment. Do you have any idea how
> the PCI-Bridge chip will behave? Are there any chances for a correct
> behavior of the system?
> I saw that Intel recommends to connect always the P_VIO pin to +5V (to
> avoid some performance problems). In the document "21154 PCI-to-PCI
> Bridge Specification Update March 2002", page 19, it is written: "P_VIO
> and S_VIO set the value of the voltage clamp only and has no effect on
> the signaling levels of the bus".
> Thank you!