RE: PCI 66MHz 5V Signaling environment?

["Phipps, Michael" <michael.phipps@intel.com>]

> I thought the problem with the Intel clamping was on the BC version
> of the bridge.

That's true.

Then a different problem showed up in the BE that also used the same
work around for many different reasons.

> I didn't check myself, but are you sure that comment about P_VIO applies
> to the BE version you mentioned. ("performance" means "signal integrity"
below?)
> (errata 4, in the intel doc)

Errata 4 (BC) was signal integrity.  Errata 9 (BE) was performance.

Performance due to an internal miscompare resulting in many retry
operations.
Didn't lose data but did get lower performance.

> (people can feel free to chime in about the BC version. I'm interested
> in other people's experience with it's clamping issues)

We aren't making the AC/BC parts now. It would still be good historical
data.

	Mike Phipps
	Intel Corp.

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> Hello!
>  
> I have to design a PCI motherboard with the Intel21154BE PCI bridge on
> it. The primary PCI bus has to work at 66MHz (64bits) and the secondary
> PCI bus at 33MHz (32bits).
> My problem is that our customer requires for the primary PCI bus a
> signaling environment of 5V (VI/O = +5V, PCI connectors 64bit, 5V). This
> would be against the PCI Local Bus Specification, which says that a PCI
> 66MHz bus uses a +3.3V signaling environment. Do you have any idea how
> the PCI-Bridge chip will behave? Are there any chances for a correct
> behavior of the system?
>  
> I saw that Intel recommends to connect always the P_VIO pin to +5V (to
> avoid some performance problems). In the document "21154 PCI-to-PCI
> Bridge Specification Update March 2002", page 19, it is written: "P_VIO
> and S_VIO set the value of the voltage clamp only and has no effect on
> the signaling levels of the bus".
>  
> Thank you!
> Laurentiu
>