RE: FIFO interface to PCI

[Irv Negrin <Negrin@flarion.com>]

Barry,

I would also recommend using the bus mastering PLX.  Using the DMA engine in
the 9054 to do the transfer makes for a real clean system architecture with
minimal CPU overhead.  If you run the DMA in demand mode, data will only
transfer when it's available in the fifo.  You have the CPU set-up the DMA
engine after it's allocated the memory on the PC side, setup a
scatter/gather descriptor chain and then kick off the transfer.  The DMA can
be programmed to send an interrupt to the CPU when the transfer is
completed.

I've done a similar design using Intel's 960RP PCI bridge with embedded 960
core about 4 years ago and achieved video transfer rates better than 40
Mbytes/sec with little burden on the CPU.

Irv.  

-----Original Message-----
From: Faust, Barry [mailto:BFaust@opex.com]
Sent: Friday, July 26, 2002 2:47 PM
To: 'pci-sig@znyx.com'
Subject: FIFO interface to PCI


Hi,

I am designing a PCI board to capture video data from a contact-image-sensor
(CIS) and transfer the data to PC memory. I am planning to use FIFOs to
uninterleave and buffer the data, then start a PCI data transfer. The data
from the CIS is a 10 MByte/sec rate. My question:  is a PCI target chip
(such as PLX 9030) adequate to support this transfer rate? I was originally
going to use a bus-master chip (PLX 9054) but didn't see the need for
another bus master (the PC's PCI bus has a master already.)  Since I am a
newcomer to the PCI world, I don't know the pros and cons of using a slave
(target) chip versus a bus-master chip.

---Barry Faust
   Opex Corp.