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RE: FIFO interface to PCI
I would tend to disagree that the PLX9030 can transfer 10Mbytes/second
using a host processor to read the data directly. You would need
2.5Mreads/second, so about 10 clock cycles per read access.
And since you aren't reading data from a prefetchable source, each read
transaction would have to change clock domains in the plx9030 twice, and
arbitrate for the backend bus on the PLX9030. And the host processor
can't initiate read transactions more often that about every 7 clock
cycles (assuming read data is immediately available).
Basically, you would be lucky to get 1 32-bit word transferred every
15-20 clock cycles. So you need to go for a bus mastering chip.
On Fri, 26 Jul 2002, Joseph Brcich wrote:
> the PLX9030 will most likely handle the data rate. However, the data will need to be moved by the processor thus tying up CPU bandwidth and reducing overall system performance.
> I recommend you use a bus master chip. This will free up the CPU to do other task while the video data is transferred.
> -----Original Message-----
> From: Faust, Barry [mailto:BFaust@opex.com]
> Sent: Friday, July 26, 2002 11:47 AM
> To: 'firstname.lastname@example.org'
> Subject: FIFO interface to PCI
> I am designing a PCI board to capture video data from a contact-image-sensor
> (CIS) and transfer the data to PC memory. I am planning to use FIFOs to
> uninterleave and buffer the data, then start a PCI data transfer. The data
> from the CIS is a 10 MByte/sec rate. My question: is a PCI target chip
> (such as PLX 9030) adequate to support this transfer rate? I was originally
> going to use a bus-master chip (PLX 9054) but didn't see the need for
> another bus master (the PC's PCI bus has a master already.) Since I am a
> newcomer to the PCI world, I don't know the pros and cons of using a slave
> (target) chip versus a bus-master chip.
> ---Barry Faust
> Opex Corp.
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