RE: PLL in PCI mode.

["Ingraham, Andrew" <Andrew.Ingraham@hp.com>]

There are at least three good reasons why a PLL doesn't work in the 33MHz PCI Environment.

(1)  The clock frequency can be anywhere from 0Hz to 33.333MHz.  No PLL can do that.

When's the last time I saw one stop its clock?  I don't know ... but I wouldn't put it past a laptop to throttle the clock speeds down occasionally to save power.

But it doesn't matter if you've seen one or not.  If your device does use a PLL, and doesn't meet this spec, it would be "creative marketing" and a lot of lying to claim that it complies with PCI.

(2)  The clock needn't even be periodic.  It just needs to meet the min/max cycle time and min pulsewidth requirements.  For whatever reason, the system COULD use a gated clock, a logic signal, skip cycles, or whatever.

(3)  In 33MHz PCI mode, unlike 66MHz mode, Spread Spectrum dithering is unconstrained.  A PLL that works on one system's SSC could fail miserably on another, because the dithering frequency happens to be lower, or it has wider modulation (bigger jitter).

Andy