Fwd: Re: FIFO interface to PCI

["Vashek Weis" <vashek@ast.co.il> (by way of Daniel Weaver <dan.weaver@znyx.com>)]

Hi,

I am afraid that Marco's comment is partially not correct. You must allocate a memory space for your FIFO to be able to build a DMA descriptor for the PLX PCI 9054. The size is irrelevant as long as it is at least the size of the block you want to transfer in single DMA transaction. You do not need to decode the local bus address, you may provide CS for the FIFO using any high order Local address signal.

You cannot burst or DMA from / to I/O (and configuration) address space and you cannot allocate more than 256 bytes of I/O address space.

Cheers,
Vashek
========

Resent-Date: Mon, 29 Jul 2002 07:24:19 -0700
Date: Mon, 29 Jul 2002 16:22:44 +0200
From: Marco Brambilla <marco-tpa.brambilla@st.com>
Organization: STMicroelectronics
To: BFaust@opex.com, pcisig <pci-sig@znyx.com>
Subject: Re: FIFO interface to PCI
Resent-From: pci-sig@znyx.com

If your device is a master, the fifo data is no longer accessible as a memory space at all.

It is the master which is picking up data from inside the fifos and move it to the system RAM.

Your only memory space will contain the configuration registers for the master.

Also, be informed that under some operating systems you may not be able to be allocated very big memory buffers, so already plan about using a linked list of buffers.

Ciao, Marco.

BFaust@opex.com wrote:
Hello all,
I would like to thank everyone who responded to my question. It sounds like
I should use a bus master chip, because the PC's processor will be very busy
processing the images. One additional question I had was whether to map the
FIFOs into memory space or I/O space. The FIFO data path is only a byte
wide. My inclination is to memory-map the FIFO accesses, then designate that
area as non-prefetchable.
---Barry

-----Original Message-----
From: Irv Negrin  [<mailto:Negrin@flarion.com>mailto:Negrin@flarion.com]
Sent: Friday, July 26, 2002 5:12 PM
To: 'pci-sig@znyx.com'
Subject: RE: FIFO interface to PCI

Barry,
I would also recommend using the bus mastering PLX.  Using the DMA engine in
the 9054 to do the transfer makes for a real clean system architecture with
minimal CPU overhead.  If you run the DMA in demand mode, data will  only
transfer when it's available in the fifo.  You have the CPU set-up the DMA
engine after it's allocated the memory on the PC side, setup a
scatter/gather descriptor chain and then kick off the transfer.  The DMA can
be programmed to send an interrupt to the CPU when the transfer is
completed.
I've done a similar design using Intel's 960RP PCI bridge with embedded 960
core about 4 years ago and achieved video transfer rates better than 40
Mbytes/sec with little burden on the CPU.
Irv.  
-----Original Message-----
From: Faust, Barry [<mailto:BFaust@opex.com>mailto:BFaust@opex.com]
Sent: Friday, July 26, 2002 2:47 PM
To: 'pci-sig@znyx.com'
Subject: FIFO interface to PCI

Hi,
I am designing a PCI board to capture video data from a contact-image-sensor
(CIS) and transfer the data to PC memory. I am planning to use FIFOs to
uninterleave and buffer the data, then start a PCI data transfer. The data
from the CIS is a 10 MByte/sec rate. My question:  is a PCI target chip
(such as PLX 9030) adequate to support this transfer rate? I was originally
going to use a bus-master chip (PLX 9054) but didn't see the need for
another bus master (the PC's PCI bus has a master already.)  Since I am a
newcomer to the PCI world, I don't know the pros and cons of using a slave
(target) chip versus a bus-master chip.
---Barry Faust
Opex Corp.



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