RE: FIFO interface to PCI

["Thomas Oelsner" <oelsner@quicklogic.com>]

Hi Barry,

Another way to accommodate your transfer requirements from your streaming
data video input is the use the QL5064 from QuickLogic. 
This device has build-in data construction logic, that for streaming data
applications allow data to packed efficiently into on-chip FIFO "on-the-fly"
and prior to activating/initiating any DMA transfer. You can set minimum or
maximum data amount to be packed into FIFO prior to each DMA transfers, this
will give you a good usage of the PCI bus bandwidth. The device works both a
32-bit, 64-bit and at 33MHz and 66MHz.

In addition to this, you can store large chaining descriptor tables within
the device's embedded memory in such a way, that your host prior to your
first transfer loads a large descriptor table to the device's "local"
on-chip memory, and then start the DMA chaining sequence. During consecutive
DMA chaining events, the device can be customized to automatically
update/maintain the active chaining descriptor table for long sustained DMA
chaining transfers without interference from the host CPU. This will safe
you PCI clock cycles between consecutive DMA chaining events and give you a
good utilization of the PCI bus bandwidth. 

For further information, please check
http://www.quicklogic.com/home.asp?PageID=319&sMenuID=203

Regards,
Thomas Oelsner




-----Original Message-----
From: Joseph Brcich [mailto:jbrcich@juniper.net]
Sent: Friday, July 26, 2002 8:42 PM
To: Faust, Barry; pci-sig@znyx.com
Subject: RE: FIFO interface to PCI


Barry

the PLX9030 will most likely handle the data rate. However, the data will
need to be moved by the processor thus tying up CPU bandwidth and reducing
overall system performance.

I recommend you use a bus master chip. This will free up the CPU to do other
task while the video data is transferred.
Regards
Joe
 
-----Original Message-----
From: Faust, Barry [mailto:BFaust@opex.com]
Sent: Friday, July 26, 2002 11:47 AM
To: 'pci-sig@znyx.com'
Subject: FIFO interface to PCI


Hi,

I am designing a PCI board to capture video data from a contact-image-sensor
(CIS) and transfer the data to PC memory. I am planning to use FIFOs to
uninterleave and buffer the data, then start a PCI data transfer. The data
from the CIS is a 10 MByte/sec rate. My question:  is a PCI target chip
(such as PLX 9030) adequate to support this transfer rate? I was originally
going to use a bus-master chip (PLX 9054) but didn't see the need for
another bus master (the PC's PCI bus has a master already.)  Since I am a
newcomer to the PCI world, I don't know the pros and cons of using a slave
(target) chip versus a bus-master chip.

---Barry Faust
   Opex Corp.

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