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Re: Retry and Parity.

To: pci-sig@znyx.com
Subject: Re: Retry and Parity.
From: "Richard Iachetta" <iachetta@us.ibm.com>
Date: Wed, 31 Jul 2002 13:14:31 -0500
Resent-Date: Wed, 31 Jul 2002 11:21:45 -0700
Resent-From: pci-sig@znyx.com
Resent-Message-ID: <3-N95B.A._-H.emCS9@electra>
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>What should PERR# signal highlight in case of parity error for a Retry
>situation on the bus? Suppose A master were to issue request and it gets
>retried and the data never got transferred, but a parity error has occured
>is it valid for us to assert PERR#?

The PAR signal must be qualified with being in an address phase or data
phase.  There is no data phase in a retry transaction so there can be no
data parity error.  The transaction may still have an address parity error
though.

Rich Iachetta
IBM Microelectronics Division -- Austin
World Wide Field Design Center
Phone: 512-838-6305   Tie Line: 678-6305

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