Re: Retry and Parity.

["Kevin Brace" <kevinbraceusenet@hotmail.com>]

>From: "Richard Iachetta" <iachetta@us.ibm.com>
>To: pci-sig@znyx.com
>Subject: Re: Retry and Parity.
>Date: Wed, 31 Jul 2002 13:14:31 -0500
>
>
> >What should PERR# signal highlight in case of parity error for a Retry
> >situation on the bus? Suppose A master were to issue request and it gets
> >retried and the data never got transferred, but a parity error has 
>occured
> >is it valid for us to assert PERR#?
>
>The PAR signal must be qualified with being in an address phase or data
>phase.  There is no data phase in a retry transaction so there can be no
>data parity error.  The transaction may still have an address parity error
>though.
>
>Rich Iachetta
>IBM Microelectronics Division -- Austin
>World Wide Field Design Center
>Phone: 512-838-6305   Tie Line: 678-6305
>
>
>


Rich,

If the initiator immediately asserts IRDY# after the address phase (IRDY# = 
'L'), the target which claims the transaction with medium DEVSEL# decode, 
inserts wait cycles for 4 cycles (DEVSEL# = 'L', TRDY# = 'H', and STOP# = 
'H'), and finally signals a retry (DEVSEL# = 'L', TRDY# = 'H', and STOP# = 
'L'), wouldn't you say that the both devices will be in the data phase for 
at least 6 cycles? (2 + 4)


Kevin Brace

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos: 
http://photos.msn.com/support/worldwide.aspx