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Re: Retry and Parity.
<kevinbraceusenet@h To: email@example.com
Subject: Re: Retry and Parity.
07/31/02 03:36 PM
>>From: "Richard Iachetta" <firstname.lastname@example.org>
>>Subject: Re: Retry and Parity.
>>Date: Wed, 31 Jul 2002 13:14:31 -0500
>> >What should PERR# signal highlight in case of parity error for a Retry
>> >situation on the bus? Suppose A master were to issue request and it
>> >retried and the data never got transferred, but a parity error has
>> >is it valid for us to assert PERR#?
>>The PAR signal must be qualified with being in an address phase or data
>>phase. There is no data phase in a retry transaction so there can be no
>>data parity error. The transaction may still have an address parity
>If the initiator immediately asserts IRDY# after the address phase (IRDY#
>'L'), the target which claims the transaction with medium DEVSEL# decode,
>inserts wait cycles for 4 cycles (DEVSEL# = 'L', TRDY# = 'H', and STOP# =
>'H'), and finally signals a retry (DEVSEL# = 'L', TRDY# = 'H', and STOP#
>'L'), wouldn't you say that the both devices will be in the data phase for
>at least 6 cycles? (2 + 4)
Kevin, I guess I was using "data phase" a little loosely forgetting that it
has a specific meaning in PCI. I should have said "data transfer" which
requires IRDY and TRDY to both be asserted. There can be no data parity
error without a data transfer. Although PERR is legally allowed to begin
to assert before the data transfer, the device doing the asserting must
know in advance that it is going to transfer data. For example, if a
target detects a write parity error before it is ready to assert TRDY (IRDY
is already asserted), the target is allowed to begin asserting PERR before
it asserts TRDY. But if it decides to do that, it must assert TRDY.
Nagesh was asking specifically a retried transaction and the target is not
allowed to assert PERR and then retry the transaction. See section
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