RE: Device at address 0

["O'Shea, David J" <david.j.oshea@intel.com>]

This thread has become overly long.

The request below 1Mbyte has little to do with whether
a device may be assigned an address of zero.  That was
for legacy opROM region requests, and those never resulted
in a zero base address.  Even when requesting a large 
allocation, a device can still get assigned zero if the 
configurator so chooses.

Zero base addresses are LEGAL!   If your device cannot
accomadate a zero base address, its designed improperly.
Most devices on the market are likely designed improperly.

The impact on Intel architecture systems is pretty much
zero, or as some folks have said "positive" in terms of
violating this aspect of the specification on Intel architecture
systems.  (The positive aspect comes from VERY MUCH older IA systems
that had poorly written system BIOS on them, which depend
on a BAR==0 as a disable function.   Current system BIOS do
not have this dependency, as they generally follow the spec).

The place where NOT following the specification, and designing
your system such that BAR=0 is disabled gets you into trouble
is on other CPU architecture systems that might want to assign
your device to address 0.  

Truthfully, on some custom IA system designs, one want to assign
a PCI device to address 0, if that device hosted memory.  Or for
debugging purposes, again a "custom" system BIOS might want to 
assign a zero address.

In general, people should follow the specification, which specifies
that all addresses are legal (including 0), and that enable/disable
is controlled by the "command" register, using the I/O and memory space
enable bits.  That is not only what the specification actually says,
it is what was intended by the specification.

The specification is multi-architecture friendly, and it is intended
and written such that zero as a base address register assignment
is LEGAL!

-David O'Shea
Intel Corp.




-----Original Message-----
From: Parampalli, Niranjana [mailto:niranjana.parampalli@intel.com]
Sent: Friday, August 02, 2002 4:10 PM
To: 'wen-king@myri.com'; pci-sig@znyx.com
Subject: RE: Device at address 0


Wen,

Further down that paper (2.1 to 2.2 Change summary),
highlighting changes in Chapter 6 it says..
  "...Devices will not be allowed to request
   memory space below the 1 Meg (Software will
   continue to support requests from pre-2.2
   devices.)"

But then it did not make it 2.2, I guess!

-n.p.

-----Original Message-----
From: wen-king@myri.com [mailto:wen-king@myri.com]
Sent: Friday, August 02, 2002 3:21 PM
To: pci-sig@znyx.com
Subject: RE: Device at address 0


In PCI 2.1 spec, section 3.2.2 at the end of the text box titled
"Implementation Note: Device Address Space", the last sentence says: A
base address register does not contain a valid address when it is equal
to "0".

In PCI 2.2 spec, in the same section and same text box, the sentence is
removed.  If its removal means having an all-0 address is now valid, it
would means it is now impossible for a card to be simultaneously
compliant to 2.1 and 2.2.
What happened?  I must have missed something.  I searched the PCISIG
web site, and looked into "2.1 to 2.2 Change summary", and I don't see
a mention of this change.

PDF file on http://www.pcisig.com/specifications/conventional_pci

It says something about 3.2.2 being re-written for improved readability,
but nothing to imply any functional changes of that sort.  I wish I
could "diff" the electronic versions of the specs.

								- Wen