[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: DEVSEL#

1. For a read cycle, Master must not drive AD/CBEJ after address phase
    because Target may drive valid data after the address cycle.
    If Master still drive these buses after address cycle, collision will
occurs and the data will be corrupted.
    So, Target should latch the address/command at address cycle only.
2. Your company must be a member of PCISIG for you to download the spec from
PCISIG web.
    However, if your company is not a member, there are several good PCI
books (ex. MindShare's PCI Architecture).
    You can get one for reference.

Best Regards

Miller Lin
Genesys Logic, Inc.
Tel:  886-2-26646655x317
Fax: 886-2-26645757