RE: PCI Interrupts

["O'Shea, David J" <david.j.oshea@intel.com>]

The Interrupt Acknowledge cycle was basically put into the specification
to support the 8259 interrupt controller on x86 PC's.  It can be used by
other systems if they wish, each use is essentially architecture dependent.

On x86 systems, with 8259, the 8259 would signal an interrupt using a 
shared signal INTR.  The cpu would respond by "implicitly" reading the
8259 by issuing a set of IntAck cycles.  (Two of them, because two
8259's were used in cascaded fashion in IBM PC AT's and later systems).

This later migrated to a single IntAck cycle, and when the PCI bus
was introduced "in between the CPU and the 8259" in PCI based chipsets,
the PCI IntAck cycle was specified to handle the job.

The INTR signal is still triggered by the 8259, and the CPU then obtains
the interrupt vector associated with the interrupt event by issuing an
IntAck cycle, which is essentially a special case "read" command of the
interrupt vector data of the interrupt controller.

The intiator drives the C/BE# signals for command "IntAck", and the expected
byte enables in the "read response from the target (the interrupt
controller).

The target samples the byte enables, and the fact that the command is
IntAck to determine that it (the Interrupt controller) is implicitly the
target of the command on the PCI bus.  (No provision is made for two
"system"
controllers to respond to IntAck).    The interrupt controller responds with
the interrupt vector on the byte enable lanes specified by the
initiator.....

This method is still used to today on all systems when they boot in
8259 interrupt controller mode.   A take off on this is used in x86
systems in XAPIC mode in some circumstances.

In order to do anything useful with this, you have to have the details
on the hostbridge/CPU and the interrupt controller semantics for your
system.   Typically, unless you are designing a new interrupt controller,
or a bridging device that will try and bridge interrupts, you don't need
to really know how this works.

-David O'Shea




-----Original Message-----
From: Paul Miranda [mailto:paul.miranda@amd.com]
Sent: Thursday, August 08, 2002 3:23 PM
To: Paul Capes
Cc: PCISIG
Subject: Re: PCI Interrupts


I don't know if other systems use it, but x86 PC systems have a Programmable

Interrupt Controller that responds to IACK cycles with a 8-bit Vector to 
identify the code to execute for the active interrupt. PCI doesn't specify a

required relationship between interrupt lines and Vectors, that's left to 
the system designer. In a PC we do what the IBM PC would have done, or more 
specifically, what the 8037 (?) does.

Paul Capes wrote:

> Hi all.
> 
> In Rev. 2.2 of the PCI spec, Figure 3-19 shows an Interrupt Acknowledge
> Cycle with something labelled 'VECTOR" driven on the AD bus. The is no
> other information I can find as to what this is or how it is supposed to
> work. I'm familiar with vectored interrupts from the Mot 68K
> architecture, but was of the impression that there was no vectoring in
> PCI. Is this supported by anyone and if so, how is it implemented?
> Thanks.
> 
> --
> Paul Capes
> 
> Engineering
> Interactive Circuits and Systems Ltd.
> 5430 Canotek Road
> Ottawa, Ontario
> Canada K1J 9G2
> Tel (613) 749-9241
> Fax (613) 749-9461
> Email pcapes@ics-ltd.com
> 
> 
> 


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