Control signal driving question

[wen-king@myri.com]

I have a question about the timing of output enables for the pads
connected to the control signals of the PCI bus.  In a bus cycle
where my PCI component has control of over a control signal, say
the STOP_ signal during a cycle when my component is the target,
do I have to keep the pad enabled the whole time?

That is,

1) If I will never assert STOP_, do I have to bother with its
   output enable at all?

2) If I do assert STOP_, do I have to actively drive a 1 onto
   the bus line prior to the time I start to assert STOP_?

3) If I do assert FRAME_ (STOP_ is a bad example in this case),
   do I have to keep driving 1 onto that bus line after I have
   driven it to 1 for one clock cycle?

I am trying to simplify my logic, and all my EE background tells me
it is OK to turn off the output enable when a control signal is
in the '1' state, as there are pull up resistors to keep it from
drifting when nobody is driving.

The spec doesn't seems to say explicitly if it is OK or not, although
the appendix B state machine seems to imply the output enables are to
be asserted for the whole time.


							- Wen