compliance checklist question

[Toshi Isogai <tisogai@seakr.com>]

Hello All,

Alan Deikman suggested me to send this e-mail to pci-sig instead
of pci-com for more response. Please execuse me if you have seen
this e-mail already in pci-com list.

******


Then, Item 2 would mean

 clk 1:  TRDY#  asserted 
 clk 2:   TRDY# deasserted ( aka released ),  wait state.
 clk 3:  TRDY# asserted

This initial TRDY assertion is not allowed for read operation because
the cycle is a turn-around cycle, is it?



On Tue, 24 Sep 2002 11:08:03 -0500
David Duxstad <dux@ieee.org> wrote:

> Toshi:
>   This is a multi-data phase transaction.  So this it would be something
> like:
> 
> clk 2:  TRDY#  asserted
> clk 3:   TRDY# deasserted ( aka released ),  wait state.
> clk 4:  TRDY# asserted
> Toshi Isogai wrote:
> 
> > Hello,
> >
> > I am having a hard time to understand one of scenario in the checklist.
> > For Master device, Test Scenario 1.8 Multi-Data Phase & TRDY# Cycles
> > Item 3 states:
> >
> >   "Verify that data is written to primary target when TRDY# is released
> >   after 3rd rising clock edge and asserted on 4th rising clock edge after
> >   FRAME#"
> >
> > Does this mean the target is not driving TRDY until 3rd edge? If so,
> > what is this test trying to verify? Pulled-up high or driven high
> > does not make any functional difference for the receiving master device. I
> > have read Addendum A for description but I still don't have any idea.
> > Can anybody advise me on this?
> >
> > Thanks.
> >
>
-- 
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Toshi Isogai          tisogai@seakr.com

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