Since I have been burnt several times by strange host power sequences messing of my PCI add-in card, I am now very cautious to heed all the warnings. Motorola's MPC8245 has more warning then most (see below).
The "Input voltage (V IN ) must not be greater than the supply voltage (Vdd/AVdd/AVdd2) by more than 2.5 V at all times including during power-on reset" - warning worries me the most. Vdd/AVdd/AVdd2 are the MPC8245 core voltages (2V) that I generate from the host system's 3.3V rail.
I know that most PCI signals are tri-stated during reset, but I am not sure about their behavior during power-on reset. Are the PCI signals specified during power-up?
I have seen "diode voltage sourcing trees" that tie 5V to 3.3V (via 3 diode drops) then 3 more diode drops to Vcore. I am a little worried about putting diodes across the host system's 3.3V and 5V power rails. Is this a safe method for add-in cards?
Am I being overly cautious?
Any other suggestions?
MPC8245 Voltage warnings from table 2 of the MPC8245 hardware spec:
5. Input voltage (V IN ) must not be greater than the supply voltage (Vdd/AVdd/AVdd2) by more than 2.5 V at all times including during power-on reset. Input voltage (V IN ) must not be greater than GVdd/OVdd by more than 0.6 V at all times including during power-on reset.
6. OVdd must not exceed Vdd/AVdd/AVdd2 by more than 1.8 V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
7. Vdd/AVdd/AVdd2 must not exceed OVdd by more than 0.6 V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8. GVdd must not exceed Vdd/AVdd/AVdd2 by more than 1.8 V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9. LVdd must not exceed Vdd/AVdd/AVdd2 by more than 5.4 V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10. LVdd must not exceed OVdd by more than 3.0 V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences
In my design:
LVdd = VIO
GVdd/Ovdd = 3.3V
Vdd/AVdd/AVdd2 = 2V generated from 3.3V
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* Corey Anderson
* corey.anderson@motioneng.com, 805.879.0585, 805.681.3311 Fax
* Motion Engineering, Inc,
* 33 S. Patera Lane, Santa Barbara, CA 93117
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