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I'm designing an interface to a PCI target core and I have several 32 bit
registers that I have mapped in the I/O space. These registers can only be
written/read via single accesses (no burst).
While simulating my PCI environment I was unable to generate a single word
read. Although this seems to be a limitation of the simulator master model,
I am wondering if it is possible to guarantee that a master will never
attempt to burst from an I/O location. This would imply that accesses to a
particular I/O location would always be master terminated after the first
In general is it necessary to provide a method for target disconnect on
registers which cannot be accessed as part of a burst?