Actel PCI Core

["Alex Horvath" <ach@sigpro.com>]

Anyone use the Actel PCI core?

I have been struggling with this core trying to simulate for a week now. I
just realized that the problem is that they delay the clocks internally to
the various modules using a VHDL 'after' statement. Since the interface I
wrote has no delay, my signals "got in front" of the clock and made the core
backend outputs either come out too early or not work at all.

I can compensate for this but I have to wonder why someone would use an
'after' statement in synthesizeable code. Also, nowhere is it documented
that one must put a delay on the backend interface signals.

At least they put a delay as opposed to just a clock signal assignment. In
that case they would just have a simulation "delta" which is almost
impossible to find.

In frustration,

Alex