Re: Actel PCI Core

["Sushant S Ranade" <sushantsr@myw.ltindia.com>]

** Proprietary **

hi Alex,

yes, i have also experienced serious problems with actel, but its tool related.

correct, 'AFTER' statement is not synthesizeble, so how can Acte PCI core
can use it? and which synthesis tool support its using?

well, which clock u r using? the clock provided by the Actel Core or direct PCI clock?
u must be using the clock provided by the core interface, then i think all the signals
should be synchronized to the clcok. if the core is not giving the synchronous signls,
its a serious problem. (unless mationed seperately for perticular asynchronoys functionality)

anyway, I think this is purely the back-end interface related problem,
better u contact the Actel design group.

Best-of-Luck,
-- Sushant

>>> "Alex Horvath" <ach@sigpro.com> 10/22/02 11:31PM >>>
Anyone use the Actel PCI core?

I have been struggling with this core trying to simulate for a week now. I
just realized that the problem is that they delay the clocks internally to
the various modules using a VHDL 'after' statement. Since the interface I
wrote has no delay, my signals "got in front" of the clock and made the core
backend outputs either come out too early or not work at all.

I can compensate for this but I have to wonder why someone would use an
'after' statement in synthesizeable code. Also, nowhere is it documented
that one must put a delay on the backend interface signals.

At least they put a delay as opposed to just a clock signal assignment. In
that case they would just have a simulation "delta" which is almost
impossible to find.

In frustration,

Alex