RE: Actel PCI Core

["Alex Horvath" <ach@sigpro.com>]

I think they were trying to compensate for VHDL clock signal assignment.
When you assign a clock such as

clk1	<= clk2;

then clk1 will be a "delta" behind clk2. Thus if have registers transferring
data and the transmitter is clocked with clk2 and the receiver is clocked
with clk1, the receiving register will appear to be transparent. Early in my
career I learned that you never assign a clock in VHDL (at least when both
sides of the assignment are used for logic).

You can "fix" the problem above by delaying clk2,

clk2_d <= clk2 after 1ns;

but to me this is adding fuel to the fire because you may have a problem
going the other way.

-----Original Message-----
From: Sushant S Ranade [mailto:sushantsr@myw.ltindia.com]
Sent: Tuesday, October 22, 2002 9:52 PM
To: pci-sig@znyx.com
Subject: Re: Actel PCI Core


** Proprietary **

hi Alex,

yes, i have also experienced serious problems with actel, but its tool
related.

correct, 'AFTER' statement is not synthesizeble, so how can Acte PCI core
can use it? and which synthesis tool support its using?

well, which clock u r using? the clock provided by the Actel Core or direct
PCI clock?
u must be using the clock provided by the core interface, then i think all
the signals
should be synchronized to the clcok. if the core is not giving the
synchronous signls,
its a serious problem. (unless mationed seperately for perticular
asynchronoys functionality)

anyway, I think this is purely the back-end interface related problem,
better u contact the Actel design group.

Best-of-Luck,
-- Sushant

>>> "Alex Horvath" <ach@sigpro.com> 10/22/02 11:31PM >>>
Anyone use the Actel PCI core?

I have been struggling with this core trying to simulate for a week now. I
just realized that the problem is that they delay the clocks internally to
the various modules using a VHDL 'after' statement. Since the interface I
wrote has no delay, my signals "got in front" of the clock and made the core
backend outputs either come out too early or not work at all.

I can compensate for this but I have to wonder why someone would use an
'after' statement in synthesizeable code. Also, nowhere is it documented
that one must put a delay on the backend interface signals.

At least they put a delay as opposed to just a clock signal assignment. In
that case they would just have a simulation "delta" which is almost
impossible to find.

In frustration,

Alex