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Re: AW: PCI Memory/IO Address Mapping...
hello Andreas,
Thnx for ur reply.. but i would appreciate it if u
could pls clarify some points that u made in ur post
to me...
>""After reading the DEV and VEN ID the BIOS writes
>0xFFFFFFFF to each base address register and read the
>value back. For all lines your card will decode the
>card has to deliver the '1's, for all internal used
>address lines it has to deliver '0's. With >this
"trick" the BIOS could determine your required >memory
size.
my doubt:
1. How exactly is this trick done internally? how is
it that when all 1s are written the values get changed
and different values r returned... are they already
stored somewhere by the pci device (is the config reg
used to store this temporary data? or is this
hardwired somewhere??) so as to supply it when a
"config read" from the BIOS to the BAR is detected? if
thats the case how does the device know that the bios
is doing this just once (ie, this writing of 1s to
allocate address ranges...) and will a re-assignment
of address range take place if the bios after startup
time tries to do the same to the device while running
(i dont know -- it doesn't need to do that for any
reason maybe!!)..
2. is it that the BIOS does a "config write" (of all
1s) and a "config read" (of the address range) in the
process of assigning the address range.
3. also how is it that it is only after the BIOS
writes 1s to the BAR, that the valid address range is
written to the BAR by the deivce... where is the
algorithm for this action/sequence of actions present?
Sorry for my insignificant queries...
Thanks again,
regards
abraham
--- "Heiner, Andreas" <HeinerA@Becker.de> wrote:
>
>
>
> Hi Abraham,
>
> You should first see the differences between ISA and
> PCI, then try to
> evaluate what is to do.
>
> The major differences are:
>
> A)
> ISA has fixed address mappings (mostly set by
> jumpers on the board) except
> PnP. Each Component has to decode its address
> (distributed address decoding)
>
> PCI has a distributed address decoding, too. But it
> is not configurable by
> jumpers, no fixed address are valid (except some old
> relicts from the ISA
> world like VGA)
>
> For this difference PCI has the Base address
> registers. They store the upper
> bits of the address the card has to decode (replaces
> the jumpers). This
> register is a requirement (at least one has to be
> implemented). The
> assignment is done in the PC world from the
> (PCI-)BIOS, in other worlds like
> QNX there are PCI-Server processes to do this.
> To assign this address, the BIOS needs some
> information. First of all the
> vendor and device id. This is the first read the
> BIOS do. Therefore it uses
> the configuration cycles. In this cycle the bus
> command (C/BE-Lines) for
> config read is set AND only one device is selected
> with the help of the
> IDSEL signal. The selected device takes the lower
> 10bit of the address and
> delivers the requested data to the host bridge. The
> ease the generation of
> the idsel signal, the upper address lines are used.
> Each device /or Slot) is
> connects its IDSEL to one of the upper address
> lines. By changing the
> address, the host bridge now can access each device.
>
> After reading the DEV and VEN ID the BIOS writes
> 0xFFFFFFFF to each base
> address register and read the value back. For all
> lines your card will
> decode the card has to deliver the '1's, for all
> internal used address lines
> it has to deliver '0's. With this "trick" the BIOS
> could determine your
> required memory size. For example: if the BIOS reads
> back the value
> 0xFF000000 you will decode the upper 8 bits, while
> using 24bit internally.
> This means you will need an address range of
> 16MByte. Then the BIOS will
> give a valid address range and writes the decoder
> bits the BAR. From now on
> your card is accessable inside the PCI system
> directly by its address.
> The BIOS will do this for each possible device
> (depends on the available
> IDSEL lines), for all BAR's and for all Busses
> (connected with
> PCI-to-PCI-Bridges).
> If your card needs an interrupt it is the same for
> the interrupt register.
> The BIOS reads the wish of your card, looks if it
> can it fulfil and assign
> this (or another possible) value to the Interrupt
> line register.
> You see, you need VEN ID and DEV ID and BAR and
> INT-Line.
>
> B)
> ISA has a common DMA controller
>
> PCI has distributed DMA controller.
>
> This means, if you has used the DMA controller in
> the ISA system, you must
> do this by yourself in the device by designing a bus
> master device. This
> device can access the bus directly, for example to
> write data directly into
> the memory of the cpu. If you don't need DMA you can
> design a target only
> device.
>
> C)
> ISA is a standard electrical bus.
>
> PCI is a reflecting wave bus.
>
> This means, the the system lives from reflections at
> the line ends. The
> avoid damage the slew rates and driver strength is
> strongly limited. Also
> there must be some overshoot diodes inside the
> device. This requires PCI
> compliant devices. By the way just one pin is
> allowed to be connected to bus
> (by ISA this was different).
> You would need special devices or design your own
> ASIC. I assume you don't
> want to design an ASIC? In this case you have to
> take either common bridge
> devices (PLX, AMCC) or FPGA's (ALTERA, XILINX). In
> the later case you case
> either write your own VHDL code, get one from
> www.opencores.org or buy a
> special core from the vendors (it is not such
> expensive). In all cases the
> required registers are available inside the devices
> and you can use the
> Vendor IDs of such vendors (in the other case you
> have to go into the
> PCISIG, pay and get an own vendor id).
>
> I hope this helps a liitle bit.
>
> Regards,
>
> Andreas
>
>
>
>
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