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RE: PERR# and SERR#
Thanks to everybody for the responses.
From: Ingraham, Andrew [mailto:Andrew.Ingraham@hp.com]
Sent: Monday, November 11, 2002 4:59 AM
Subject: RE: PERR# and SERR#
> Why are some signals in PCI like TRDY#, IRDY#, FRAME# etc categorised
> Sustained tristate signals? What makes them different?
Most of the control signals, TRDY#, IRDY#, FRAME#, etc., have meaning on
every cycle; whereas the AD signals are meaningful only on "qualified"
cycles where they transfer Address or Data.
These "sustained tri-state" control signals are required to have pull-up
resistors so that they remain negated (high) even during turn-around
cycles when no PCI agent drives them.
The AD signals can be high or low or in between during turn-around
cycles and it doesn't matter.
> Why is PERR# a STS (sustained tristate signal) signal, while SERR# an
> open-drain signal?
PERR# is driven by only one PCI device at a time, the one that has
SERR# can be driven by any PCI device on any cycle.
In CMOS, the usual way to implement a signal that any device can assert
at any time, is to make it open-drain with a pull-up resistor. Then it
doesn't matter if one device, no device, or all devices drive it low;
and nobody ever drives it high. An STS signal wouldn't do because one
device might be driving it high while another drives it low.