PCI clock routing

[Tak-kwong Ng <t.k.ng@larc.nasa.gov>]

Hi all,

I read in this discussion forum that the PCI standard only allows PCI CLK 
signal to be routed to only one load. I am working on a satellite 
application and I can't locate a clock buffer that would survive the harsh 
radiation environment. I am using a FPGA core for the pci interface. Will 
routing CLK to two adjacent FPGA pins violate the standard ? Thanks.

Tak-kwong Ng
MS 488
Langley Research Center, NASA
5 N Dryden St
Hampton, VA 23681
Phone: 757-864-1097 Fax: 757-864-7944