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Interrupt Disable bit



Hi,
 
Does anyone know how the Interrupt Disable bit in the Command register, introduced in PCI 2.3 is intended to be used?
 
 
Thanks,
 
Jim Lindeman
Principal Engineer, ASICs
JNI Corporation
45365 Northport Loop West
Fremont, CA 94538-6417 
direct +1.510.360.4714
fax +1.510.252.0123
jlindeman@jni.com
www.jni.com