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FW: Interrupt Disable bit



Hi Jim,
 
I asked the same question some time ago, and here is the response I received:
 
Matthew Myers
Synopsys
 
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Hi Matt,
Many devices function as expected.  Some will get into a mode where they will generate an abnormally high rate of interrupts.  The interrupt rate prevents the system from performing its normal function.  After rebooting the system, it will function normally for several days before the interrupt storm occurs again making it very difficult to identify the source of the abnormally high rate of interrupts (interrupt sharing adds to the difficulty of identifying the source of the interrupts).  The Interrupt Disable and Interrupt Status bits will allow the system to determine the source of the interrupt storm by disabling interrupts on devices until the interrupt storm is terminated.

Regards,
Richard
---- Don't miss the 3GIO and PCI-X 2.0 techanical training at the June 3-4, 2002 PCI Developers Conference (see http://www.pcisig.com/events/devcon) ------
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From: Matthew Myers [mailto:Matthew_Myers@insilicon.com]
Sent: Tuesday, March 26, 2002 12:01 PM
To: 'administration@pcisig.com'
Subject: Question about PCI 2.3 Interrupt masking

Hi there,

I am curious about the reasoning behind the new interrupt mask and
status bits in PCI 2.3 - what application was envisioned when it was
decided that this should be added to the spec?

If the ECN explains this, could you please point me to the ECR/ECN
regarding the new interrupt masking/status capability?

Thanks,
Matt
-----Original Message-----
From: Jim Lindeman [mailto:JLindeman@jni.com]
Sent: Thursday, November 14, 2002 11:43 AM
To: pci-sig@znyx.com
Subject: Interrupt Disable bit

Hi,
 
Does anyone know how the Interrupt Disable bit in the Command register, introduced in PCI 2.3 is intended to be used?
 
 
Thanks,
 
Jim Lindeman
Principal Engineer, ASICs
JNI Corporation
45365 Northport Loop West
Fremont, CA 94538-6417 
direct +1.510.360.4714
fax +1.510.252.0123
jlindeman@jni.com
www.jni.com