[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

RE: Interrupt Disable bit



The configuration software (BIOS or OS) would disable the generation of interrupts,
unless a driver or opROM enables them in an OS or BIOS POST.
 
e.g.  Device interrupt generation is disabled, an opROM loads and the device opROM
enables interrupts via the command register.
 
e.g.  Device interrupt generation is disabled by BIOS in POST, and an OS loads.  The
OS loads a device driver for the for the device, and in finding an appropriate device driver,
either enables the interrupt for the PCI device on driver load, or enables the interrupt for
PCI device when the driver uses the OS IRQ handler registration mechanism.
 
The intent is to prevent devices from generating IRQ's until they have a device driver
loaded that can handle them, since IRQ's are shared.    Otherwise, a device may not
be using its IRQ, but since the IRQ is generated - and shared- with other devices,
those device see unnecessary calls to their IRQ handlers, as the software system searches
for the owner of the IRQ event.   (But there wasn't one, becuase no driver is loaded,
or the driver isn't using the IRQ....)
 
Allowing the software subsystem to disable IRQ generation in the device solves the issue-
and that is the point of the Interrupt Disable bit in the command register.
 
-David O'Shea
Enterprise Products and Services Division, Intel Corp.
-----Original Message-----
From: Jim Lindeman [mailto:JLindeman@JNI.com]
Sent: Thursday, November 14, 2002 11:43 AM
To: pci-sig@znyx.com
Subject: Interrupt Disable bit

Hi,
 
Does anyone know how the Interrupt Disable bit in the Command register, introduced in PCI 2.3 is intended to be used?
 
 
Thanks,
 
Jim Lindeman
Principal Engineer, ASICs
JNI Corporation
45365 Northport Loop West
Fremont, CA 94538-6417 
direct +1.510.360.4714
fax +1.510.252.0123
jlindeman@jni.com
www.jni.com