RE: PCI clock routing

["Ingraham, Andrew" <Andrew.Ingraham@hp.com>]

> I read in this discussion forum that the PCI standard only allows PCI
> CLK 
> signal to be routed to only one load. I am working on a satellite 
> application and I can't locate a clock buffer that would survive the
> harsh 
> radiation environment. I am using a FPGA core for the pci interface.
> Will 
> routing CLK to two adjacent FPGA pins violate the standard ? Thanks.
 
Technically, yes, if it is on a standard form factor PCI card.

The one-load restriction applies to components on a PCI plug-in
expansion card.  If it's on a motherboard or system board, it doesn't
apply.

If you are designing this for a PCI plug-in card, and if you know
exactly where this thing will go (i.e., your market is strictly
limited), you can probably "bend the rules" because you can verify that
it works correctly in the intended environment, i.e., every motherboard
/ plug-in card situation.  Just don't turn around and sell the card to
the general public.

Regards,
Andy