RE: 3.3V FPGA with 5V PCI..?

["Ingraham, Andrew" <Andrew.Ingraham@hp.com>]

Using 3.3V-powered buffers for 5V PCI signaling, is not uncommon.  The
5V signaling electrical requirements are rather broad and do allow
signal levels as low as 2.4V to be driven.

Yes, it is OK to do this.

Are there any other concerns?  One is that the I/Os need to tolerate not
only 5V levels from other buffers that do drive 5V, but overshoot which
might reach double that, in the absence of clamping.  Pay attention to
the "Maximum AC Ratings and Device Protection" sections, which say your
buffers need to withstand certain test waveforms.

Clamping above 5V, though not mandatory, is desirable to help control
overshoot and ringing.

Many older motherboards do not provide 3.3V power to the PCI connectors
(in a 5V signaling environment).  Because of that, most PCI add-on cards
with 3.3V-powered components, had to regulate their own 3.3V.
Motherboards that comply with Rev. 2.2 specs do provide 3.3V power to
connectors.

And don't be tempted to use these buffers in a 3.3V PCI signaling
environment.  If the I/Os are tolerant of 5V levels, they do not meet
the requirements for 3.3V signaling, unless you can program some on-chip
overshoot clamp diodes to start clamping above 3.3V when used in the
3.3V environment.  There are buffers that can do this, but many do not.

Regards,
Andy


> ----------
> We are using an FPGA based local to PCI bridge whose I/O is in 3.3V
> but with input tolerance of 5V. The PCI side of the bridge is supposed
> to work with a standard 5V PCI add-on card. PCI local specs. 2.2  DC
> specification (page 117) for 5V signaling indicates that input high –
> min is 2.0 V. 
> Is this design OK ? Is there any other parameter to be considered as
> far as 3.3V FPGA hosting 5V add-on card is considered ?