Query on ECC in PCI X 2.0

[Vibarajan V <viba@sasken.com>]

Hi,

We are implementing a PCI X 2.0 design. We have some couple of doubts
with respect to the ECC impelementation.

When ECC is calculated for the data phase, there comes the data phase
protection stage. The spec. says that every data phase corresponds to
a phase address. Based on the phase address, the phase protection is
selected and EXORed to generate the final ECC.

The questions are about the data phase address:

Q.#1 Is the PHASE address starts with 0 always for any burst or
     any other transaction?

                      (OR)

     it starts from the starting address that was issued during the
     address phase of the transaction?

Q.#2 How the PHASE address increments for every data phase?
     Does it incremtn by one count irrespective of the bus width (16,
     32, and 64)?

                       (OR)

     it increments based on the no. of bytes (Ex: 4 bytes for 32 bits
     width) like data_phase_address + 4 (for 32 bit width)?

     Ex:

      next_data_phase_address = present_data_phase address + 4;
                           
I request your help to clarify this issue.

Thanks,
Vibarajan.V
Sr.H/W engineer,
Sasken COmmunication Tech. Ltd.,
Bangalore - 560 008
India
Ph: +91-80-5355501, 02, 03, Ext: 8192.
Email: <viba@sasken.com>