Address Decoding in PCI

[bhanupratap bandaluppi <bhanupratap_b@yahoo.com>]

Hi all,
1.For memory transactions in PCI AD bus, AD[31:2]
contains the dword aligned address. For checking if
this is in range with Base Address Register, we need
to compare both of them.
But base address register has 31:4 bits only for
address decoding. How do we compare both of them? 
Suppose if we need maximum memory size of 1 GB, do we
need to implement two base address registers? why?
2.For IO transactions specification says upper 16 bits
of BAR should be hardwired to zero and at the same
time it says all 32 bits should be decoded. How can
this be possible?
Please explain me if possible with examples
Thanks
Bhanu

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