RE: Address Decoding in PCI

[Olaf.Reichenbaecher@sci-worx.com]

bhanu,

> 1.For memory transactions in PCI AD bus, AD[31:2]
> contains the dword aligned address. For checking if
> this is in range with Base Address Register, we need
> to compare both of them.
> But base address register has 31:4 bits only for
> address decoding. How do we compare both of them? 
> Suppose if we need maximum memory size of 1 GB, do we
> need to implement two base address registers? why?

in order to recognize a AD-BAR match you don't need to
compare ALL bits 32..2. you will just check whether
the upper bits of BAR and AD match. how much of the upper
bits need to match is determined by the size of the
address space your BAR is assigned to.
all bits that are required to address ressources within
the corresponding address space are don't care in terms
of BAR decoding.
so if you are going to implement an address space of 1GB
the bits 29:2 are needed to address a dword ressource within that
address space. you just need to check whether AD bits 31:30
do match BAR bits 31:30. of course your decoder needs to "know"
which bits to check but that's just it.

usually one doesn't need to compare bits 3:2 of AD vs. memory
BAR. one might think he needs to do so if he is going
to assign an address range of less than just 4 dword-aligned
(less than 16 byte) addresses to a memory base address space.
since that really doesn't make much sense and requires a lot
of address decoding logic the PCI spec recommends not to assign
an address space of less than 4 kbytes to a memory BAR (which
results in a decoder for bits 31:12).

> 2.For IO transactions specification says upper 16 bits
> of BAR should be hardwired to zero and at the same
> time it says all 32 bits should be decoded. How can
> this be possible?
> Please explain me if possible with examples

i guess you refer to the last paragraph on page 203:
"Devices that map control function into I/O space must not consume
more than 256 bytes per I/O Base Address register. The upper 16 bits of 
the I/O Base Address register may be hardwired to zero for devices
intended for 16-bit I/O systems, such as PC compatibles. However, a
full 32-bit decode of I/O addresses must still be done."

my understanding is in systems that do just support 16 bit I/O addresses
you are allowed to hardwire the upper 16 bits to zero. this is not
a must. you are still allowed to put your I/O address space anywhere
in the 32 bit address range. hardwiring the upper 16 bits to zero
just places the I/O address space (still in the 32 bit address range)
below the 64 kbyte boundary by default. but you are still required to
evaluate the upper 16 bits since your device may be accessed with an
I/O transaction that is directed to an I/O address space located beyond
the 64 kbyte boundary. your device is not allowed to respond in this case.
and in systems with 32 bit I/O addresses you will still have to
do a full 32 bit decoding anyway.

i hope this helps.

best regards

  olaf

-- 
Olaf Reichenbaecher
Senior Design Engineer
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sci-worx GmbH
www.sci-worx.com

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