RE: 3.3v env

["Ingraham, Andrew" <Andrew.Ingraham@hp.com>]

Yuval,

My responses below apply to conventional PCI.

You wrote:

> From the SBC manufacturer we received a data sheet indicating that VIO must be connected to VCC.(5v)
> We received from them assurance that this SBC will work in 3.3v signaling.
> So now we are confused?
 
I am confused too.  The VIO voltage always equals the PCI signaling
environment voltage.

In PCI this voltage is also known as VCC.  That is, VCC = 5V when using
5V signaling, and VCC = 3.3V when using 3.3V signaling.

Did the SBC manufacturer say that VIO must be connected to 5V, or that
it must be connected to VCC?


> 1) What will be the VIO level connected to the expansion pci64 slot ?
> Is it 3.3v from the 3.3v rail?
 
64-bit PCI can use either 5V or 3.3V signaling; thus, VIO might be
either 5V or 3.3V.


> 2) Doesn't the VIO on the expansion slots must be the same VIO on the PICMG?
> 3)If it is so how it will work on 3.3v signaling if the VIO on the PICMG is connected to the 5V?
> 4) Does the VIO to the pci slots to the 3.3v card must be separate (connected to 3.3v) from the VIO to the PICMG
> connected to VCC(5V)
 
I am not sure exactly which PICMG environment you are talking about. 
PICMG includes CompactPCI, as well as passive backplanes that use the
conventional PCI form factor.

However, *my* assumption (unless proven otherwise) would be that VIO
on each card would match the VIO on the backplane.  The two connect
together, and the VIO voltage on the card comes from the VIO voltage
on the backplane.

But also note that the "5V Signaling Environment" includes signals
that may switch only to 3.3V; that is, signals that do not switch all
the way between 0V and VIO = 5V.  Some people might call these signals
"3.3V signaling" even though they are not PCI's definition of "3.3V
signaling."

Regards,
Andy