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PCI-Express PHY Implementors
I am implementing a 16-lane PCI-Express LINK, PHY
and SERDES core looking for feedback on the newest
PCI-Express Base Specification Rev 1.0, July 22, 2002
from other implementors of the Clause 4 Physical Layer.
I am currently getting good response within the Intel
Developers Network for the PCI-Express General Forum,
but am looking for contacts within the PCI-SIG standards
body.
If a better email reflector exists, let me know.
Please contact me at curtr@lsil.com
Thanks - Curt
begin:vcard
n:Ridgeway;Curt
tel;fax:408-954-4764
tel;work:408-433-7792
x-mozilla-html:FALSE
url:www.lsilogic.com
org:LSI Logic Storage Components;Serial Protocol Development
version:2.1
email;internet:curtr@lsil.com
title:Distinguished I/O Architect, Serial Protocols
adr;quoted-printable:;;1873 Barber Lane=0D=0AMS AH-260;Milpitas;California;95035;USA
note;quoted-printable:=0D=0A
x-mozilla-cpt:;-20840
fn:Ridgeway, Curt
end:vcard