RE: Crosstalk Limit

["Ingraham, Andrew" <Andrew.Ingraham@hp.com>]

Hi Ramesh,

> What is the cumulative crosstalk limit for PCI signals at 3.3v and 5v?
>
> Cumulative crosstalk is the total crosstalk from all adjacent lines to one
> victim line if the same aggressor signal is applied to all adjacent lines.
 
The specification does not have a crosstalk limit.

Ultimately, what matters is that every signal should have valid logic
levels at all input pins, at each rising edge of the CLK.  Actually,
they should be valid during a window that surrounds CLK, bounded by
Tsu before CLK, and Th after CLK.

Valid means they should meet the input voltage requirements, Vih or Vil.

The thing about crosstalk from other PCI bus signals, is that this is
a synchronous bus.  Almost everything switches at a time when input
signals are not being clocked in and do not need to be valid.  With
few exceptions, the aggressors are switching when the victims are
being ignored and do not need to be valid.

Whether a signal is actually switching, or isn't switching but
crosstalk from other signals makes it momentarily change state, it
makes no difference.  All that matters is that the signal becomes
valid again by the Setup time before the next rising edge of CLK.

With that being the case, victim signals could tolerate several VOLTS
of crosstalk (in the right direction) without it being a problem ...
as long as the crosstalk and all lingering effects settle down again
by the next CLK.

There are exceptions.  A few PCI signals are asynchronous and can't
tolerate such wild behavior.  A momentary crosstalk glitch onto an
Interrupt line, or a CLK line, that is large enough to change state,
could be disastrous if it occurs at any time.  And crosstalk from
signals that are not synchronous to the PCI bus are always significant
because these could line up with the CLK.


There is an inherent "noise margin" in most digital logic, between the
guaranteed output logic levels and the required input levels.  In 5V
PCI, the DC noise margin is 0.25V in the low state, 0.4V in the high
state.  With 3.3V PCI, these numbers are about 0.6V and 1.2V
respectively.

The noise margin means that signals can tolerate that amount of
corruption from other sources, before a signal might not be valid
anymore.  In other words, a signal that is steady can tolerate that
amount of cumulative crosstalk (plus any other noise) and still be
received in the correct state.

But the hitch is that it is a steady-state or DC margin and doesn't
include transient effects.  When signals switch, there can be ringback
and other corruptions that can negate all of the steady-state margins.

Regards,
Andy