perr enable bit and target abort bit in status register

[bhanupratap bandaluppi <bhanupratap_b@yahoo.com>]

Hi all
1)For a target core, once we get parity error or
target abort we need to set the corresponding bits in
the status bits. When do we need to disable these
bits. Because next transaction or next dataphase might
again get the error and then what must we do? Also how
do the master access these bits. Do we need to keep
the bits set until the configuration read transaction
is done? 
2) what do the master do when a parity error is
detected?
3) For a configuration transaction, if we dont support
burst transaction, what must we do? Must we disconnect
with data???
Thanks
Bhanu

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